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Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.

Keywords: Encryption, Decryption Rijndael algorithm, FPGA implementation, Physical Design.
Title: Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASIC,
Author: Y. Navya Rao, D.Ranjith
 
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
Paper Publications

Abstract:Reactive Power Optimization is a complex combinatorial optimization problem involving non-linear function having multiple local minima, non-linear and discontinuous constrains.  This paper presents  PS2O, which extends the dynamics of the canonical PSO algorithm by adding a significant ingredient that takes into account the symbiotic co evolution between species, Hybrid Evolutionary-Conventional Algorithm (HECA) that uses the abilities of evolutionary and conventional algorithm and Genetical Swarm Optimization (GSO), combines Genetic Algorithms (GA) and Particle Swarm Optimization (PSO).All the above said algorithms is used to overcome the Problem of premature convergence. PS2O,  HECA , GSO  is applied to Reactive Power Optimization problem and is evaluated on standard IEEE 57, practical 191 test Bus Systems. The results shows that all the three algorithms perform well in solving the reactive power problem and prevent premature convergence to high degree but still keep a rapid convergence. Of all the three  PS2O has the edge in reducing the real power loss when compared to HECA & GSO.

Keywords:PS2O, Hybrid Evolutionary-Conventional Algorithm, Genetical Swarm Optimization, Reactive Power Optimization.
Title:PS2O, Hybrid Evolutionary-Conventional Algorithm, Genetical Swarm Optimization for Solving Reactive Power Optimization Problem
Author:Mr. K. Lenin, Dr. B. Ravindhranath Reddy
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
ISSN: 2349-7815
Paper Publications

Abstract:In this paper, merging Immune Genetic Particle Swarm Optimization algorithm (IGPSO) with BP algorithm to optimize BP Neural Network parameter i.e., BPIGPSO amalgamation to solve optimal reactive power dispatch algorithm. The basic perception is that first training BP neural network with IGPSO to find out a comparatively optimal solution, then take the network parameter at this time as the preliminary parameter of BP algorithm to carry out the training, finally searching the optimal solution.   The proposed BPIGPSO has been tested on standard IEEE 57 bus test system and simulation results show clearly the better performance of the proposed algorithm in reducing the real power loss.

Keywords:BP neural network, Immune Genetic Particle Swarm Optimization algorithm, Optimal Reactive Power, Transmission loss.
Title:Combination of Immune Genetic Particle Swarm Optimization algorithm with BP algorithm to solve optimal reactive power dispatch algorithm
Author:Mr.K.Lenin, Dr.B.Ravindhranath Reddy, and Dr.M.Surya Kalavathi
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
ISSN: 2349- 7815
Paper Publications